1. Field of the Invention
The present invention relates to a device for accessing at least one registered circuit unit via an access register, and, in addition, it relates to an access register which is adapted to be used for such access.
2. Description of Prior Art
One example of a scenario where access to circuit units takes place via access registers are memory modules comprising registered memory chips, e.g. DRAM memory modules (DRAM=dynamic random access memory). In the case of such memory modules, e.g. 9, 18 or 36, memory chips are arranged on the board of the memory module, control access to the memory chips being effected making use of memory registers. Inputs of the memory registers are connected to an input C/A bus (C/A=command/address) so as to receive command/address signals from a memory control. The outputs of the registers are, again via respective C/A buses, connected to the respective memory chips. The C/A buses have a predetermined number of positions, i.e. lines, the respective ports of memory registers and memory chips, which are connected to respective buses, comprising a corresponding number of inputs and outputs, respectively.
In known command/address bus architectures in a registered DDR-DIMM (DDR-DIMM=double data rate dual inline memory module) the data rate is limited due to the high input capacitance of the DRAM chips and the long connecting buses leading from the registers to many DRAM chips. In the case of existing topologies, the track length of the connecting buses between memory registers and memory chips is very long and not symmetric.
Examples of existing command/address bus architectures are shown in FIGS. 3 and 4.
FIG. 3 shows nine memory units 1 to 9 formed e.g. by nine memory chips which are arranged on the board of a memory module. In the architecture shown, the nine memory chips are arranged side by side in groups of five memory chips and four memory chips, memory registers 10 and 12 being arranged between the groups. The respective second contours, which are shown in FIG. 3 and one of which is, by way of example, designated by 1′, are shown for indicating that a corresponding arrangement of nine memory chips may be provided on a second surface of a memory module board so that the memory module comprises a total of eighteen memory chips. The two access registers 10 and 12 each have a number of register inputs connected to lines of a register input bus 14. The register input bus is a C/A bus. For the sake of clarity, FIG. 3 shows only four lines for each register input bus 14. In reality, each register input bus 14 comprises a higher number of lines, i.e. positions, e.g. twenty-four positions.
The access registers 10 and 12 have, as is usually the case, buffer elements and drivers for driving outputs of the access registers. The outputs of the buffer registers 10 and 12 are connected to respective connecting buses 16 and 18 having the same number of lines as the register input buses 14 and representing C/A buses as well. The access registers 10 and 12 can therefore be referred to as 1/1 access registers.
The connecting bus 16 serves to connect the outputs of the access register 10 to respective inputs of the group of five memory chips 1, 2, 3, 4 and 5. The number of inputs of the respective memory chips corresponds to the number of lines of the connecting bus 16. Again for the sake of clarity, only four positions are shown with regard to the bus 16 as well as with regard to the inputs of the memory chips, although, in reality, a larger number of positions, e.g. twenty-four, is provided. The four inputs of the circuit chip 1 are, by way of example, designated by reference numeral 20. As can be seen in FIG. 3, the connecting bus 16 comprises respective branch points, one of which is, by way of example, designated by reference numeral 22, so as to connect each of the bus lines to the associated input of each of the circuit chips 1 to 5.
The connecting bus 18 has the same configuration so as to connect the outputs of the access register 12 to associated inputs of each of the memory chips 6, 7, 8 and 9. The four inputs of the memory chip 9 are, again by way of example, designated by reference numeral 24, whereas examples of branch points, which permit a bus line 28 to connect the respective output of the access register 12 to the associated inputs of the memory chips 6, 7, 8 and 9, are designated by reference numeral 26.
As can be seen in FIG. 3, five memory chips are arranged on one side of the access registers 10, 12, whereas only four memory chips are arranged on the other side thereof. In order to compensate different bus lengths resulting from this dissymmetry, a compensation point 30 is provided in the connecting bus 18 so as to compensate the otherwise shorter line lengths of the connecting bus 18 resulting from the smaller number of memory chips with which this connecting bus establishes a connection. It follows that, in the architecture shown in FIG. 3, it is necessary to insert an additional bus length for compensation so as to produce identical electrical lengths of the connecting buses 16 and 18; in spite of this insertion of an additional bus length, a symmetry of the topology cannot be obtained.
FIG. 4 shows a further known architecture of registered memory chips; in said FIG. 4 reference numerals which are comparable to those used in FIG. 3 have been used for comparable elements. In contrast to FIG. 3, the architecture of FIG. 4 uses only one access register 32 comprising again a predetermined number of inputs, e.g. twenty-four, which are connected to a register input bus 14; for the sake of clarity, also FIG. 4 shows only four positions of the input bus and four inputs of the access register 32. The outputs of this individual access register are connected to two connecting buses 16 and 18 establishing a connection to the respective left and right groups of memory chips. Each connecting bus 16 and 18 comprises a number of positions corresponding to that of the input bus 14. Hence, the access register 32 can be referred to as 1/2 access register, since it provides a division of an input bus 14 comprising a predetermined number of positions into two output buses 16, 18 comprising each the same predetermined number of positions.
In the case of the example shown in FIG. 4, the problem of different track lengths of the connecting buses 16 and 18 has to be solved in the same way as in the case of the example shown in FIG. 3, so that a compensation point 30, which provides an additional track length, is again provided in the connecting bus 18. However, a symmetric topology cannot be achieved in this case either.
In addition to the above-described asymmetric topologies, the architectures described with reference to FIGS. 3 and 4 have long track lengths of the connecting buses 16 and 18. This increases, on the one hand, the access time to the memory chips, which are controlled via the connecting buses 16 and 18, and, on the other hand, it reduces the signal quality of the signals transmitted via the connecting buses.